Analog Circuits Questions and Answers – Low Frequency Response and Miller Effect Capacitance

 This set of Analog Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Low Frequency Response and Miller Effect Capacitance”.

1. In Miller’s theorem, what is the constant K?

a) Total voltage gain

b) Internal voltage gain

c) Internal current gain

d) Internal power gain

View Answer

Answer: b

Explanation: The constant K=V2/V1, which is the internal voltage gain of the network.

Thus resistance RM=R/1-K

RN=R/1-K-1.

2. When applying miller’s theorem to resistors, resistance R1 is for node 1 and R2 for node 2. If R1>R2, then for same circuit, then for capacitance for which the theorem is applied, which will be larger, C1 or C2?

a) C1

b) C2

c) Both are equal

d) Insufficient data

View Answer

Answer: a

Explanation: Given R1>R2

R/1-K > R/1-K-1, and so 1-K-1>1-K

Thus K2>1, K>1, K<-1 (correct)

Thus, C1=C(1-K) and C2=C(1-K-1)

Hence C1>C2

3. Find net voltage gain, given hfe = 50 and hie = 1kΩ.

analog-circuits-questions-answers-low-frequency-miller-effect-capacitance-q3

a) 27.68

b) -22

c) 30.55

d) -27.68

View Answer

Answer: d

Explanation: Apply millers theorem to resistance between input and output.

At input, RM=100k/1-K = RI

Output, RN=100k/1-K-1 ≈ 100k

Internal voltage gain , K = -hfeRL’/hie

K = – 50xRc||100k/1k = – 50x4x100/104= – 192

RI = 100k/1+192 = 0.51kΩ

RI’ = RI||hie = 0.51k||1k = 0.51×1/1.51 = 0.337kΩ

Net voltage gain = K.RI’/RS+RI’ = – 192 x 0.337/2k + 0.337k = -27.68.

4. Given that capacitance w.r.t the input node is 2pF and output node is 4pF, find capacitance between input and output node.

a) 0.67 pF

b) 1.34pF

c) 0.44pF

d) 2.2pF

View Answer

Answer: a

Explanation: C1=C(1-K), C2=C(1-K-1)

C1=2pF

C2=4pF

C1/C2=1/2=1-K/1-K-1

K = -2

C1 = C(1+2) = 3C

C = C1/3 = 2/3pF = 0.67 pF.

5. Consider an RC coupled amplifier at low frequency. Internal voltage gain is -120. Find the voltage gain magnitude, when given that collector resistance = 1kΩ, load = 9kΩ, collector capacitance is 0. is 0.1μF, and input frequency is 20Hz.

a) 120

b) 12

c) 15

d) -12

View Answer

Answer: c

Explanation: AV = -120

fL = 1/2πCC(RC+RL) = 1/2π*0.001 = 1000/2π = 159.15Hz

AV’ = |AV|1√+(fLf)2

AV’ = 120/8.02 ≈ 15.

6. Find the 3-dB frequency given that the gain of RC coupled amplifier is 150, the low frequency voltage gain is 100 and the input frequency is 50Hz.

a) 50.8 Hz

b) 55.9 Hz

c) 60Hz

d) 100Hz

View Answer

Answer: b

Explanation: AVM = 150

AVL = 100

f = 50Hz

100 = 1501√+(fL50)2

1+f2/2500 =1.52

f2 = 2500*1.25 = 3125

f = 55.90 Hz.

7. Given collector resistance = 2kΩ, load resistance = 5kΩ, collector capacitance = 1μF, emitter capacitance = 20μF, collector current = 2mA, source resistance = 2kΩ. If the effect of blocking capacitor is ignored, find the applicable cut-off frequency.

a) 22.73 Hz

b) 612 Hz

c) 673Hz

d) 317 Hz

View Answer

Answer: b

Explanation: RC = 2kΩ, RL = 5kΩ, CC = 1μF, CB = 10μF, CE = 20μF, RS = 2 kΩ

hie = 1kΩ, IC = 2mA

fL1 = 1/2πCC(RC+RL) = 22.73 Hz

fL2 = gm/2πCE = IC/2πCEVT = 612 Hz

Since fL2 > 4fL1, hence fL2 is the correct answer.

8. Consider the circuit shown.

analog-circuits-questions-answers-low-frequency-miller-effect-capacitance-q8

hfe = 50, hie = 1000Ω. Find magnitude of voltage gain at input frequency 10Hz.

a) 100

b) 133

c) 166

d) 220

View Answer

Answer: b

Explanation: Net load = 10k||10k = 5kΩ = RL’

AVM = -hfeRL’/hie = -50×5/1 = -250

fL = 1/2πCC(RC+RL) = 15.9 Hz

AVL = AVM1√+(fLf)2 = 133.

9. What is the phase shift in RC coupled CE amplifier at lower 3dB frequency?

a) 180°

b) 225°

c) 270°

d) 100°

View Answer

Answer: b

Explanation: Total phase shift = 180°+ tan-1(fL/f)

At 3dB frequency fL/f = 1

Total phase shift = 180° + 45° = 225°.

10. Consider that the phase shift of an RC coupled CE amplifier is 260°. Find the low frequency gain when the voltage gain of the transistor is -150.

a) 100

b) 26

c) 40

d) 55

View Answer

Answer: b

Explanation: 180° + tan-1(fL/f) = 260°

fL/f = tan(80) = 5.67

A = 1501√ + 5.672 = 26.05.

Analog Circuits Questions and Answers – Effect of Various Capacitors on Frequency Response – 2

 This set of Analog Circuits Mcqs focuses on “Effect of Various Capacitors on Frequency Response – 2”.

1. Ignoring early effect, if R1 is the total resistance connected to the base and R2 is the total resistance connected at the collector, what could be the approximate input pole of a simple C.E. stage?

a) 1 / [R1 * (Cµ(2+gm*R2) + Cπ)]

b) 1 / [R1 * (Cµ(1+2*gm*R2) + Cπ)]

c) 1 / [R1 * (Cµ(1+gm*R2) + Cπ)]

d) 1 / [R1 * (Cµ(1-gm*R2) + Cπ)]

View Answer

Answer: c

Explanation: The input pole can be approximately calculated by observing the input node. The input node is the node where the base of the B.J.T. is connected to the input voltage. The product of total resistance and capacitance connected at that particular node is R1 * Cin and Cin is Cµ(1+gm*R2) + Cπ- the inverse of this product gives us the input pole. Thus the correct option is 1 / [R1 * (Cµ(1+gm*R2) + Cπ)].

2. Ignoring early effect, if R2 is the total resistance at the collector, what could be the approximate output pole of a simple C.E. stage?

a) 1 / [R2 * (Ccs + Cµ*(1 + 2/gm*R2))]

b) 1 / [R2 * (Ccs – Cµ*(1 + 1/gm*R2))]

c) 1 / [R2 * (Ccs + Cµ*(1 – 1/gm*R2))]

d) 1 / [R2 * (Ccs + Cµ*(1 + 1/gm*R2))]

View Answer

Answer: d

Explanation: The output pole can be approximately calculated by observing the output node. For a C.E. stage, the output node is the node where the Collector of the B.J.T. is connected to the output measuring device. The product of total resistance and capacitance connected at that particular node is R2 * Cout and Cout is (Ccs + Cµ*(1 + 1/gm*R2). The inverse of this product gives us the output pole. Thus the correct option is 1 / [R2 * (Ccs + Cµ*(1 + 1/gm*R2))].

3. If the load resistance of a C.E. stage increases by a factor of 2, what happens to the high frequency response?

a) The 3 db roll off occurs faster

b) The 3 db roll off occurs later

c) The input pole shifts towards origin

d) The input pole becomes infinite

View Answer

Answer: a

Explanation: If the load resistance increases by a factor of 2, the output pole decreases since it’s inversely proportional to the load resistance. Hence the C.E. stage experiences a faster roll off due to the pole.

4. During high frequency applications of a B.J.T., which of the following three stages do not get affected by Miller’s approximation?

a) C.E.

b) C.B.

c) C.C.

d) Follower

View Answer

Answer: b

Explanation: During the C.B. stage, the capacitance between the base and the collector doesn’t suffer from Miller approximation since the input is applied to the emitter of the B.J.T. There are no capacitors connected between two nodes having a constant gain. Hence the C.B. stage doesn’t get affected by miller approximation.

5. Ignoring early effect, if C1 is the total capacitance tied to the emitter, what is the input pole of a simple C.B. stage?

a) 1/gm * C1

b) 2/gm * C1

c) gm * C1

d) gm * 2C1

View Answer

Answer: a

Explanation: The resistance looking into the emitter of the B.J.T. is 1/gm. The capacitance connected to the input node is C1 (as mentioned). The inverse product of these two provides us the input pole of the C.B. stage.

6. Ignoring early effect, if R1 is the total resistance connected to the collector; what is the output pole of a simple C.B. stage?

a) 1/[R1 * (Ccs + Cµ)]

b) 1/[R1* (Ccs + 2*Cµ)]

c) 1/[R1 * (2*Ccs + Cµ)]

d) 1/[R1 * 2*(Ccs + Cµ)]

View Answer

Answer: a

Explanation: The output pole is calculated, approximately, by the inverse product of the total resistance and the capacitance connected at the output node. We find that the total resistance connected to the output node is R1 while the total capacitance is Ccs + Cµ. In absence of early effect, 1/[R1 * (Ccs + Cµ)] becomes the output pole.

7. If early effect is included, and R1 is the total resistance connected at the collector. What is the output pole of a simple C.B. stage?

a) 1/[(R1 || ro) * 2(Ccs + Cµ)]

b) 1/[(R1 || ro) * (Ccs + Cµ)]

c) 1/[(R1 || ro) * (2*Ccs + Cµ)]

d) 1/[(R1 || ro) * 2*(Ccs + 2*Cµ)]

View Answer

Answer: b

Explanation: The output pole is calculated, approximately, by the inverse product of the total resistance and the capacitance connected at the output node. We find that the total resistance connected to the output node is R1 in parallel with ro, due to early effect, while the total capacitance is C2 ie Ccs + Cµ. Thus, the correct option is 1/[(R1 || ro) * (Ccs + Cµ)].

8. In a simple follower stage, C2 is a parasitic capacitance arising due to the depletion region between the collector and the substrate. What is the value of C2?

a) 0

b) Infinite

c) Ccs

d) 2*Ccs

View Answer

Answer: a

Explanation: During the high frequency response, the capacitor between the collector and the substrate gets shorted to A.C. ground at both of its terminals. Hence, C2=0. The answer would have been Ccs for any other stage of B.J.T.

9. For a cascode stage, with input applied to the C.B. stage, the input capacitance gets multiplied by a factor of ____

a) 0

b) 1

c) 3

d) 2

View Answer

Answer: d

Explanation: The small signal gain, of the C.B. stage, in a cascode stage is approximately equal to the ratio of the transconductances of the two B.J.T.’s. Since they are roughly same, the gain is 1. Miller multiplication leads to multiplying the capacitance, between base and collector, by a factor of (1 + small signal gain) which is 2. Hence, the correct option is 2.

10. If the B.J.T. is used as a follower, which capacitor experiences Miller multiplication?

a) Cπ

b) Cµ

c) Ccs

d) Cb

View Answer

Answer: a

Explanation: We find that the input is given to the base of the B.J.T. while the output is sensed at the collector of the B.J.T. We observe that the only capacitance connected between two nodes- where there is an amplification unit between the nodes, is Cπ. Hence, the correct option is Cπ.

11. If 1/h12 = 10 for a C.E. stage- what is the value of the base to collector capacitance, after Miller multiplication, at the output side?

a) 1.1Cµ

b) 1.2Cµ

c) 2.1Cµ

d) 2.2Cµ

View Answer

Answer: a

Explanation: At the output side of a C.E. stage, Cµ gets multiplied by a factor of (1+1/Av) where Av is the voltage gain. 1/h12 is nothing but Av. Hence, the value changes to 1.1Cµ.

12. If 1/h12 = 4, for a C.E. stage- what is the value of the base to collector capacitance, after Miller multiplication, at the input side?

a) 4Cµ

b) 5Cµ

c) 6Cµ

d) 1.1Cµ

View Answer

Answer: c

Explanation: The capacitor, Cµ, gets multiplied by a factor of (1 + Av), at the input side of a C.E. stage. 1/h12 is equal to Av since h12 is the reverse voltage amplification factor. Hence, the final value becomes 5Cµ.

13. The transconductance of a B.J.T.is 5mS (gm) while a 2KΩ (Rl) load resistance is connected to the C.E. stage. Neglecting Early effect, what is the Miller multiplication factor for the input side?

a) 21

b) 11

c) 20

d) 0

View Answer

Answer: b

Explanation: The Miller multiplication factor for the input side of a C.E. stage is (1+Av). Now, Av is the small signal low frequency gain of the C.E. stage which is gm*RL=10. Hence, the Miller multiplication factor is 11.

Analog Circuits Questions and Answers – Effect of Various Capacitors on Frequency Response – 1

 This set of Analog Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Effect of Various Capacitors on Frequency Response – 1”.

1. During high frequency applications of a B.J.T., which parasitic capacitors arise between the base and the emitter?

a) Cje and Cb

b) Ccs

c) Cb

d) Ccs and Cb

View Answer

Answer: a

Explanation: There are two capacitors which arise between bases and emitter. One is Cje due to depletion region associated between base and emitter. Cb is another capacitor which arises due to the accumulation of electrons in the base which further results into the concentration gradient within the base of the transistor.

2. During high frequency applications of a B.J.T., which parasitic capacitors arise between the collector and the emitter?

a) No capacitor arises

b) Ccs

c) Cb

d) Ccs and Cb

View Answer

Answer: a

Explanation: The emitter and the collector are far away from each other when the B.J.T. is being constructed. Hence, we find that they don’t share a common junction where charges can accumulate. Thus, no such parasitic capacitors appear.

3. During high frequency applications of a B.J.T, which parasitic capacitors arise between the collector and the base?

a) Cje and Cb

b) Ccs

c) Cπ

d) Cµ

View Answer

Answer: d

Explanation: Only one capacitor up between the base and the collector. This is due to the depletion region present between the base and the collector region.

4. Which parasitic capacitors are present at the collector terminal of the B.J.T.?

a) Cje and Cb

b) Ccs and Cµ

c) Cb

d) Ccs and Cb

View Answer

Answer: b

Explanation: There are two capacitors attached to the collector terminal. The collector-base junction provides a depletion capacitance (Cµ) while the collector substrate junction provides a certain capacitance (Ccs).

5. Which parasitic capacitors do not affect the frequency response of the C.E. stage, of the B.J.T.?

a) Cje and Cb

b) Ccs and Cµ

c) Cb and Cµ

d) No parasitic capacitor gets deactivated

View Answer

Answer: d

Explanation: While observing the frequency response of a C.E. stage, we find that all the parasitic capacitances of the B.J.T. end up slowing the speed of the B.J.T. The frequency response of this stage is affected by all the parasitic capacitors.

6. Which parasitic capacitors don’t affect the frequency response of the C.B. stage of the B.J.T.?

a) None of the parasitic capacitances

b) All the parasitic capacitances

c) Some of the coupling capacitors

d) Ccs and Cb

View Answer

Answer: b

Explanation: All the parasitic capacitors of a B.J.T. affect the C.B. stage. None of the parasitic capacitors gets deactivated and they end up behaving as a pole during the frequency response of the C.B. stage.

7. Which parasitic capacitors don’t affect the frequency response of the C.C. stage of the B.J.T.?

a) Ccs

b) Ccs and Cb

c) Cb

d) Ccs and Cµ

View Answer

Answer: a

Explanation: In the follower stage, the load is present at the emitter. The parasitic capacitors present between the collector and the substrate i.e. Cµ gets deactivated. This is observed from the small signal analysis where both the terminals of this capacitor get shorted to A.C. ground.

8. If the transconductance of the B.J.T increases, the transit frequency ______

a) Increases

b) Decreases

c) Doesn’t get affected

d) Doubles

View Answer

Answer: a

Explanation: The transit frequency is directly proportional to the transconductance of the B.J.T. Hence, the correct option is increases. Since it hasn’t been mentioned that whether the transconductance has been doubled or not, we cannot conclude the option “doubles” as an answer.

9. If the total capacitance between the base and the emitter increases by a factor of 2, the transit frequency __________

a) reduces by 2

b) increases by 2

c) reduces by 4

d) increases by 4

View Answer

Answer: a

Explanation: The transit frequency is almost inversely proportional to the total capacitance between the base and the emitter of the B.J.T. Hence, the transit frequency will approximately reduce by 2 and the correct option becomes reduces by 2.

10. Which effect plays a critical role in producing changes in the frequency response of the B.J.T.?

a) Thevenin’s effect

b) Miller effect

c) Tellegen’s effect

d) Norton’s effect

View Answer

Answer: a

Explanation: The miller effect results in a change in the capacitance seen between the base and the collector. This is why, it affects the frequency response of the B.J.T. deeply by changing the poles and affecting the high frequency voltage gain stage.

11. If a C.E. stage has a load Rl and transconductance gm, what is the factor by which the capacitance between the base and the collector at the input side gets multiplied?

a) 1 + gmRl

b) 1 – gmRl

c) 1 + 2*gmRl

d) 1 – 2*gmRl

View Answer

Answer: a

Explanation: The low frequency gain of the C.E. stage is gmRl. By the application of miller effect, we find that the capacitor between the base and the collector, looking into the input of the C.E. stage, will be increased by a factor of 1 + gmRl.

12. If a C.E. stage has a load Rl and transconductance gm, what is the factor by which the capacitance between the base and the collector at the output side gets multiplied?

a) 1 + 1/gmRl

b) 1 – 1/gmRl

c) 1 + 2/gmRl

d) 1 – 2/gmRl

View Answer

Answer: a

Explanation: The low frequency response of the C.E. stage is gmRl. By the application of miller effect, we find that the capacitance between the base and the collector, looking from the output side, will be increased by a factor of 1 + 1/gmRl. Hence, the correct option is 1 + 1/ gmRl.

13. If a C.E. stage with early effect has a load Rl and transconductance gm, what is the factor by which the capacitance between the base and the collector at the output side, gets multiplied?

a) 1 + 2/gm*(Rl || ro)

b) 1 – 1/gm*(Rl || ro)

c) 1 + 1/gm*(Rl || ro)

d) 1 – 2/gm*(Rl || ro)

View Answer

Answer: c

Explanation: If the early effect is considered, the low frequency response of the C.E. stage becomes gm*(Rl || ro). Thereby, miller approximation shows that the capacitance between the base and the collector, looking from the output side, will be increased by a factor of 1 + 1/gm*(Rl || ro). Hence the correct option is 1 + 1/ gm*(Rl || ro).

14. For a high frequency response of a simple C.E. stage with a transconductance of gm, what is Cin?

a) Cµ(1 + gm*R2) – Cπ

b) Cµ(1 + gm*R2) + Cπ

c) Cµ(1 – 2*gm*R2) + Cπ

d) Cµ(1 + 2*gm*R2) – Cπ

View Answer

Answer: b

Explanation: The input capacitance is an equivalent of the base to emitter capacitance in parallel to the miller approximation of the base to collector capacitance. Due to miller approximation, the base to collector capacitance becomes Cµ(1+gm*R2) while the base to emitter capacitance is Cπ. Capacitors get added, when in parallel and thus Cµ(1+gm*R2) + Cπ is correct.

15. For a high frequency response of a simple C.E. stage with a transconductance of gm, what is Cout?

a) Ccs – Cµ*(2 + 1/gm*R2)

b) Ccs + Cµ*(1 + 2/gm*R2)

c) Ccs – Cµ*(1 + 1/gm*R2)

d) Ccs + Cµ*(1 + 1/gm*R2)

View Answer

Answer: d

Explanation: We have a capacitor from the collector to substrate, Ccs, which comes in parallel to the miller approximation of the capacitance from base to collector. The miller approximation defines the latter as Cµ*(1 + 1/gm*R2). Since capacitors gets added, when in parallel, the correct option is Ccs + Cµ*(1+ 1/gm*R2).

Analog Circuits Questions and Answers – General Frequency Consideration

 This set of Analog Circuits Multiple Choice Questions & Answers (MCQs) focuses on “General Frequency Consideration”.

1. The frequency f1 and f2 from the below picture are respectively called ___________

analog-circuits-questions-answers-general-frequency-consideration-q1

a) lower cut-off frequency and upper cut-off frequency

b) upper cut-off frequency and lower cut-off frequency

c) left frequency, right frequency

d) there is no specific name

View Answer

Answer: a

Explanation: The frequencies are called lower cut-off frequency and upper cut-off frequency. At these frequencies power of the signal becomes half of its original value, 3dB less than the maximum and they are also called 3dB cut-off frequencies.

2. Bandwidth of amplifier is __________

a) Difference between upper cut-off frequency and lower cut-off frequency

b) Sum of upper cut-off frequency and lower cut-off frequency

c) Average of upper cut-off frequency and lower cut-off frequency

d) Independent to cut off frequency

View Answer

Answer: a

Explanation: 3dB bandwidth of an amplifier is the difference between upper cut-off frequency and lower cut-off frequency. The unity gain bandwidth is the difference between frequencies where gain is 1.

3. At 3dB cut-off frequency the voltage gain will be __________

a) 100% of maximum gain

b) 70.7% of maximum gain

c) 80.7% of maximum gain

d) 47.5% of maximum gain

View Answer

Answer: b

Explanation: 3dB cut-off frequency is the frequency at which the power becomes half of its maximum value. That is the voltage gain becomes 0.707 times maximum voltage gain.

4. At 3dB cut-off frequencies power will be __________

a) Half of maximum value

b) Quarter of maximum value

c) 70.7% of maximum value

d) Same as maximum value

View Answer

Answer: a

Explanation: 3dB cut-off frequency is the frequency at which the power becomes half of its maximum value. That is the voltage gain becomes 0.707 times maximum voltage gain. The importance of 3dB points is that for a human ear, it will not notice the fall in power of the signal up to 50% of maximum power.

5. A voltage amplifier has a voltage gain of 100. What will be gain at 3dB cut-off frequencies?

a) 70.7

b) 80.7

c) 45.7

d) 50

View Answer

Answer: a

Explanation: 3dB cut-off frequency is the frequency at which the power becomes half of its maximum value. That is the voltage gain becomes 0.707 times maximum voltage gain. Therefore if voltage gain is 100 then gain at 3dB frequencies will be

100 x 0.707 = 70.7.

6. What is the roll-off rate of single order filter?

a) 20dB/decade

b) 5dB/octave

c) 40dB/decade

d) 10dB/octave

View Answer

Answer: a

Explanation: At lower and higher frequencies the gain is decreasing. This fall or decrease in gain is known as roll-off rate. It is commonly specified in dB/octave or dB/decade. For a single order filter the roll-off rate is 6dB/octave or 20dB/decade.

7. -6dB is equivalent to __________ power gain.

a) 0.5

b) 0.25

c) 0.75

d) 0.8

View Answer

Answer: b

Explanation: The relation between dB and power gain is

dB = 10 log(power gain)

That is power gain for -6dB is

10(-6 /10) = 0.251.

8. Voltage gain of 1,00,000 is equivalent to __________

a) 10dB

b) 1000dB

c) 100dB

d) 50dB

View Answer

Answer: c

Explanation: dB = 20 log(voltage gain)

Therefor 100000 voltage gain is equivalent to

20 log(1,00,000)dB = 100 dB.

9. If the output power from an audio amplifier is measured at 100W when the signal frequency is 1kHz, and 1W when the signal frequency is 10kHz. Calculate the dB change in power.

a) -10dB

b) -20dB

c) -30dB

d) 15dB

View Answer

Answer: b

Explanation: The initial power gain in dB = 10 log (output power)

= 10 log(100) = 20dB

The final power gain in dB = 10 log(output power)

= 10 log(1) = 0 dB

So change in power = final power – initial power

= 0-20 = -20dB.

10. If an electronic system produces a 48mV output voltage when a 12mV signal is applied, calculate the decibel value of the systems output voltage gain.

a) 12dB

b) 6dB

c) 20dB

d) 4dB

View Answer

Answer: a

Explanation: Gain of the system is = output voltage/input voltage

= 48/12 = 4

Gain in dB = 20 log(voltage gain)

= 20 log(4) = 12.04 dB

Analog Circuits Questions and Answers – Collector Feedback Configuration

 This set of Analog Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Collector Feedback Configuration”.

1. The Collector feedback configuration is better than __________

a) Fixed Bias Configuration

b) Voltage divider configuration

c) C.E. configuration

d) C.B. configuration

View Answer

Answer: a

Explanation: The fixed bias circuit has been seen to offer low stability with respect to change in ICO. The Voltage divider bias provides the most stable biasing mechanism. Hence, the collector feedback configuration is better than the fixed bias configuration while C.E. and C.B. are not biasing stages.

2. The Collector feedback is done by connecting a resistor from the collector to the __________

a) Emitter

b) Base

c) Supply voltage

d) Bias voltage

View Answer

Answer: b

Explanation: The collector feedback configuration is done by connecting a resistor from the collector to the base voltage. This is done to stabilize the biasing voltage against thermal runaway.

3. The Collector feedback configuration helps to stabilize __________

a) Bias voltage

b) Collector voltage

c) Bias current

d) Collector current

View Answer

Answer: d

Explanation: The collector feedback configuration is used to stabilize the Collector current. The Collector current is seen to increase at a sincere rate which can harm the transistor by thermal runaway. Stabilizing this current is necessary during biasing a transistor for proper application.

4. The Collector feedback helps to evade __________

a) Inverse Active mode

b) Pinch Off

c) Thermal Runaway

d) Breakdown

View Answer

Answer: c

Explanation: The increase in the Collector current is primarily due to ICO. A sudden increase in ICO can increase the Collector current and this will increase the temperature of the device. This is called thermal runaway and duee to high current gain of the transistor, the transistor can get destroyed due to thermal runaway. The Collector feedback configuration helps to evade this phenomenon.

5. Due to the Collector feedback mechanism, the transistor remains always remains in the __________

a) Active mode

b) Saturation mode

c) Inverse Active

d) Cut-off

View Answer

Answer: a

Explanation: The collector feedback configuration helps to keep the transistor in the active region. This is done because the bias voltage can get changed if the input and the bias voltage is superposed. With the introduction of this feedback mechanism, the transistor always stays biased in the active region.

6. What are the effects on the output voltage if the Collector resistance increases in a Collector feedback configuration?

a) Not much effect

b) Bias voltage reduces

c) Bias voltage increases

d) Bias voltage doubles

View Answer

Answer: a

Explanation: The increase in collector resistance doesn’t have much impact on the output voltage since the bias voltage is kept stable by the feedback operation. After all, one of the important applications of feedback is increasing stability and the output voltage is kept stable by this configuration.

7. What kind of configuration is this?

analog-circuits-questions-answers-collector-feedback-configuration-q7

a) Collector feedback

b) Base Bias

c) Self Bias

d) No bias

View Answer

Answer: d

Explanation: The transistor isn’t biased since the voltage drop from the base to the collector is 0. The transistor action won’t get be manifested.

8. If the current gain of the transistor is β, what is the stability factor pertaining to IC and ICO?

analog-circuits-questions-answers-collector-feedback-configuration-q8

a) β+1/ {1 + β * R1/(R1 + β)}

b) β+1

c) β+1/ {1 + β * R2/(R1 + β)}

d) β+1/ {1 + (R1 + β)}

View Answer

Answer: a

Explanation: The stability factor is determined by calculating the change in IC with respect to the change in ICO. Hence, we can simply apply the method of K.V.L. and derive a relation between these two currents. After differentiation, we’ll get the stability factor as β+1/ {1 + β * R1/(R1 + β)}.

9. To keep the B.J.T. in the active region, what should be the relation between R1 and R2?

analog-circuits-questions-answers-collector-feedback-configuration-q8

a) R1 >> R2

b) R1 << R2

c) R1 = R2

d) No such relation

View Answer

Answer: b

Explanation: The feedback resistance should be much smaller than the collector resistance since we need to reduce the sensitivity of the collector current to the current gain. Typically, R2 should be lower than R1 by a factor of β.

10. From the base bias to the collector feedback configuration, the stability facto S reduces by a factor of __________

a) 1 + R1/(R1 + β)

b) 1 + β * R1/(R1 + β)

c) β * R1/(R1 + β)

d) R1/(R1 + β)

View Answer

Answer: b

Explanation: This can be simply observed from the stability factors of both cases. The correct factor is 1 + β * R1/(R1 + β).

11. What is the stability factor against VBE for the collector feedback configuration?

a) β / (Rc * (1 + β)

b) -β / (RB + Rc * (1 + β)

c) β / (RB + Rc * (1 + β)

d) -β / (Rc * (1 + β)

View Answer

Answer: c

Explanation: This is easily derived from the Collector feedback configuration by using the method of K.V.L. deriving a relation between the collector current and the base emitter voltage. It should be noted that the stability against VBE increases in comparison to the base bias comparison.

12. What is the condition of stability of the following circuit?

analog-circuits-questions-answers-collector-feedback-configuration-q12

a) Highly stable

b) Poorly stable

c) Marginally stable

d) Unstable

View Answer

Answer: b

Explanation: The Collector feedback configuration does make the biasing stable but here, the collector and the base resistances are same. Hence, we conclude that the circuit is poorly stable. The base resistance should be substantially lower than the collector resistance.

13. If β = 100, what should be the ratio of the collector to base resistance for achieving insensitivity to β?

analog-circuits-questions-answers-collector-feedback-configuration-q12

a) 110

b) 90

c) 20

d) 140

View Answer

Answer: d

Explanation: The Base resistance should be substantially lower than the Collector resistance by a factor of β. 110 is a good choice but provided 140 is present as an option, a better choice is a factor of 140.

14. Why are we worried about β during the Collector feedback configuration?

a) To maintain a stable q-point irrespective of β

b) To increase the gain

c) To decrease the output impedance

d) To maintain a stable input impedance

View Answer

Answer: a

Explanation: If we change the device, β changes. But we want to keep the q-point stable so that circuit if represented as a black box, would provide the same characteristics and not be highly dependent on the transistor. Hence, we want to make the circuit insensitive to β.

15. The stability factors change from npn to pnp transistor.

a) True

b) False

View Answer

Answer: b

Explanation: The stability factors are independent of whether the transistor is of npn or pnp type. It is only dependent on β and the impedance connected to the terminals of the transistor.uation of a hyperbola.

Analog Circuits Questions and Answers – Hybrid Equivalent Model

 This set of Analog Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Hybrid Equivalent Model”.

1. Which of the following statement is incorrect?

a) Output of CE amplifier is out of phase with respect to its input

b) CC amplifier is a voltage buffer

c) CB amplifier is a voltage buffer

d) CE amplifier is used as an audio (low frequency) amplifier

View Answer

Answer: c

Explanation: The output of the CE amplifier has a phase shift of 180o with respect to the input. The CC amplifier has AV≅1, thus it is a voltage buffer. However, the CB amplifier has a large voltage gain, and its current gain AI≅1, thus it is a current buffer. CE amplifier has an application has an audio amplifier.

2. Consider the following circuit. __________ provides DC isolation. _____________ prevents a decrease in voltage gain. _____________ is used to control the bandwidth.

analog-circuits-questions-answers-hybrid-equivalent-model-q2

a) C3, C1, C4

b) C4, C1, C2

c) C2, C3, C2

d) C4, C3, C2

View Answer

Answer: b

Explanation: Capacitor C3 and C4, are the blocking capacitor and coupling capacitor respectively, both providing DC isolation to biasing circuit. Capacitor C1 is the emitter bypass capacitor, to prevent decrease in voltage gain by avoiding negative feedback. Capacitor C2 is the shunt capacitor, used to control the bandwidth, wherein the bandwidth is inversely proportional to C2.

3. Given hfe = 60, hie=1000Ω, hoe = 20μ Ω–, hre = 2 * 10-4. Find the current gain of the BJT, correct up to two decimal points.

analog-circuits-questions-answers-hybrid-equivalent-model-q3

a) – 58.44

b) -59.21

c) – 60.10

d) – 60.00

View Answer

Answer: a

Explanation: Current gain, AI = – hf / (1 + hoRL’) where RL’ = 2kΩ||4kΩ

RL’ = 1.33kΩ.

Thus AI = – 60 / (1 + 0.0266) = -58.4453.

4. Consider the circuit. Given hfe = 50, hie = 1200Ω. Find voltage gain.

analog-circuits-questions-answers-hybrid-equivalent-model-q4

a) – 278

b) -277.9

c) – 300

d) – 280

View Answer

Answer: a

Explanation: Voltage gain = AV = -hfeRL’/hie

RL’ = 20k||10k = 6.67kΩ

AV = -50 * 6.67k/1.2k = -277.9 ≅ – 278.

5. Given that IB = 5mA and hfe = 55, find load current.

analog-circuits-questions-answers-hybrid-equivalent-model-q5

a) 28mA

b) 280mA

c) 2.5A

d) 2A

View Answer

Answer: b

Explanation: In given circuit, which is an emitter follower, current gain = 1 + hfe

IL = IB (1+hfe)

IL = 5mA(56) = 280 mA.

6. Consider the following circuit, where source current = 10mA, hfe = 50, hie = 1100Ω, then for the transistor circuit, find output resistance RO and input resistance RI.

analog-circuits-questions-answers-hybrid-equivalent-model-q6

a) RO = 0, RI = 21Ω

b) RO = ∞, RI = 0Ω

c) RO = ∞, RI = 21Ω

d) RO = 10, RI = 21Ω

View Answer

Answer: c

Explanation: Since hoe is not given, we can consider it to be small; i.e 1/hoe is neglected, open circuited. Hence output resistance RO = ∞.

Input resistance = hie/(1 + hfe) = 1100/51 ≅ 21Ω.

7. For the given circuit, input resistance RI = 20Ω, hfe = 50. Output resistance = ∞. Find the new values of input and output resistance, if a base resistance of 2kΩ is added to the circuit.

analog-circuits-questions-answers-hybrid-equivalent-model-q7

a) RI = 20Ω, RO = ∞

b) RI = 20Ω, RO = 2kΩ

c) RI = 59Ω, RO = ∞

d) RI = 59Ω, RO = 2kΩ

View Answer

Answer: c

Explanation: RI = 20k = hie/(1+hfe) = hie/51

hie =1020 Ω

Hence, after adding base resistance, RI’= (hie+RB)/(1+hfe) = (1020+2000) / 51 ≅ 59Ω

There is no change in output resistance or current gain due to an extra base resistance. RO’ = ∞.

8. Consider its input resistance to be R1. Now, the bypass capacitor is attached, so that the new input resistance is R2. Given that hie = 1000Ω and hfe = 50, find R1-R2.

analog-circuits-questions-answers-hybrid-equivalent-model-q8

a) 112.2Ω

b) 0Ω

c) 110Ω

d) 200Ω

View Answer

Answer: a

Explanation: For the circuit, CE amplifier without bypass capacitor, input resistance, R1=hie + (1+hfe)RE

R1 = 1000 + 51*2.2 = 1000 + 112.2 = 1112.2Ω

With a bypass capacitor attached, input resistance, R2 = hie = 1000Ω

Thus R1 – R2 = 112.2Ω.

9. Given that for a transistor, hie = 1100Ω, hfe = 50, hre = 2*10-4 and hoe = 2μΩ-1. Find CB h-parameters.

a) hfb = 1, hib = 22, hob = 3μΩ-1, hrb = -1.5×10-4

b) hfb = -0.98, hib = -21.56, hob = 0.03μΩ-1, hrb = 1.5×10-4

c) hfb = -0.98, hib = 21.56, hob = 0.03μΩ-1, hrb = -1.5×10-4

d) hfb =1, hib = -21.56, hob = 0.03μΩ-1, hrb = -2×10-4

View Answer

Answer: c

Explanation: hfb = -hfe/(1+hfe) = -50/51= -0.98

hib = hie/(1+hfe) = 21.56Ω

hob = hoe/(1+hfe) = 0.03 μΩ-1

hrb = (hiehoe/1+hfe) – hre = -1.5×10-4.

10. If source resistance in an amplifier circuit is zero, then voltage gain (output to input voltage ratio) and source voltage gain (output to source voltage ratio) are the same.

a) True

b) False

View Answer

Answer: a

Explanation: When a source resistance RS is present, the voltage gain with respect to source becomes

AVS = AVRI’/(RS+RI’), where AV is voltage gain with respect to transistor input. However when RS=0 then AVS = AV.

Analog Circuits Questions and Answers – Characteristics of Amplifier

 This set of Analog Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Characteristics of Amplifier”.

1. The state amplifier has no input is not called ______________

a) Zero signal condition

b) Non-signal condition

c) Quiescent condition

d) Empty-signal condition

View Answer

Answer: d

Explanation: The state at which amplifier has zero input signal is called zero signal condition, Non-signal condition, quiescent condition. There is nothing named empty-signal condition.

2. Which of the following is not considered for quiescent operating point?

a) DC collector-emitter voltage

b) DC collector current

c) DC base current

d) DC input voltage

View Answer

Answer: d

Explanation: The quiescent point is the operating point of an amplifier where the DC condition of amplifier is constant. For that we have to make sure that DC collector-emitter voltage, DC collector current, DC base current are constant.

3. Which of the following resistor is not involving in biasing the circuit shown below?

analog-circuits-questions-answers-characteristics-amplifier-q2

a) R1

b) R2

c) RC

d) RL

View Answer

Answer: d

Explanation: R1, R2, RC are, used to bias the circuit while RL is used as a load resistor. R1, R2 are used as a voltage divider. RC is used to control collector current.

4. Which of the following statements is most correct to explain role of biasing circuit in the implementation of a transistor circuit?

a) It is used provide proper voltage to every component in the circuit

b) It is used to ensure maximum power is obtained out of the circuit

c) It is used to provide the quiescent collector current

d) It is used to provide proper and stable functional environment to all quiescent point parameters

View Answer

Answer: d

Explanation: The basic function of biasing is to maintain amplifier in quiescent condition. The amplifier will properly work only if the quiescent condition is stable.

5. What is the role of input capacitance in the transistor amplifying circuit?

a) To prevent input variation from reaching output

b) To prevent DC content in the input from reaching transistor

c) There isn’t any role for input capacitance

d) To increase input impedance

View Answer

Answer: b

Explanation: The input capacitance, as its name indicates is used to prevent DC offset voltages in the input. It also prevents the transistor bias voltage to be fed back to input generating circuit.

6. What is the role of emitter bypass capacitance in the transistor amplifying circuit?

a) To prevent damage of emitter resistance from variation in voltage

b) To prevent emitter from over voltage

c) To increase gain

d) To increase load to transistor circuit

View Answer

Answer: c

Explanation: When an emitter resistance is added to the amplifier circuit, in common emitter mode, voltage gain is reduced and input impedance increases. When we need to obtain higher gain, we add a capacitance in parallel to the emitter resistance, called emitter bypass capacitance, and voltage gain does not decrease.

7. Which of the following is actually not a function of emitter bypass capacitor?

a) Increase gain

b) Lower the impedance of emitter resistance

c) Provide a low reactance path

d) Help emitter resistance to withstand voltage variation

View Answer

Answer: d

Explanation: The emitter bypass capacitor is not meant for reducing loading effect of emitter resistance. It is to increase gain. It provides a low reactive path to the AC signal without changing the quiescent point.

8. What is the role of emitter resistance in the transistor amplifying circuit?

a) To prevent thermal runaway

b) To prevent increase in gain

c) To lower the output impedance

d) To increase gain

View Answer

Answer: a

Explanation: Thermal runaway is the increase in the collector current without an increase in input due to heating of semiconductor material which in turn reduce the resistance thus increases current. The emitter resistor decreases effective input voltage decrease when collector current increases and thus it reduces collector current itself.

9. Which of the following is not true regarding the output capacitor in the transistor biasing circuit?

a) To pass AC signal

b) To stop DC signal

c) To couple the amplifier to load or next amplifier

d) There is no importance for an output capacitance

View Answer

Answer: d

Explanation: The output capacitor or output coupling capacitor is provided to pass AC signal and to block DC signal. It also helps to couple the amplifier to load or next amplifier.

10. Which of the following is the best biasing method for transistor bias?

a) emitter bias

b) voltage divider bias

c) fixed bias

d) collector feedback bias

View Answer

Answer: b

Explanation: Voltage divider bias is more stable because the biased voltage will not change. It is best to use voltage divider bias for accuracy.